Personal Information

• Name：Kunyi Liu                      Gender：Male
• Date of Birth：2001/01/07             Email：kunyi.liu23@imperial.ac.uk

Work and Education Experience

RESEARCH& PROJECTS

1. B.S. in Shandong University - Micro/Nano Device Reliability Laboratory - Advisor: Associate Professor Yuan Li

   • Bias-independent sub-threshold swing in ballistic cold-source field-effect transistors by drain density-of-states engineering
   • Developed a novel mechanism to achieve bias-independent sub-60 mV/dec subthreshold swing (SS) in ballistic cold-source field-effect transistors (CS-FETs) for portable electronics.
   • Conducted first-principles and quantum-transport simulations to demonstrate the critical role of energy alignment of the number of conduction modes (NOCM) between drain and source electrodes in achieving bias-independent SS of C31/MoS2-based CS-FETs.
   • Proposed a device model based on the connection between NOCM and density of states (DOS) to stabilize SS of devices under different bias conditions.
   • Highlighted the significance of drain DOS engineering in the design of bias-insensitive CS-FETs for portable electronic applications.
   • Published paper in the top-tier journal in the field of applied physics, Applied Physics Letters: https://doi.org/10.1063/5.0177388

2. B.S. in Shandong University - Micro/Nano Device Reliability Laboratory - Advisor: Associate Professor Yuan Li

   • Study on the stability of hhk-silicene in contact with different metals (Graduation Thesis)
   • Hhk-silicene (a two-dimensional silicon-based semiconductor) was modeled using QuantumATK and its electrical properties were verified.
   • Modeling and relaxation optimization of the interface between the two-dimensional material and other metals
   • Calculation of formation energy and charge transfer characteristics
   • The electrical properties (band-structure, density of states) of different metals with hhk-silicene interface systems are calculated and explained in combination with charge transfer characteristics.

3. B.S. in Shandong University - Micro/Nano Optoelectronics Science and Technology - Flexible Electronics (A)

   • Constructed single-electron transistors for identifying DNA base categories
   • Adjusted device sensitivity by tuning transistor feature sizes

4. B.S. in Shandong University- Micro/Nano Optoelectronics Science and Technology - Electronic Design Automation (A+)

   • Utilized EDA Verilog programming to design a data communication system
   • Systematically learned FPGA hardware and Verilog programming using Vivado software.
   • Developed end-to-end communication systems, including serial and parallel communication.
   • Implemented audio processing using data interpolation algorithms and pitch adjustment algorithms.
   • Successfully achieved FPGA-based audio communication using Verilog programming.

5. B.S. in Shandong University- Micro/Nano Optoelectronics Science and Technology - Digital Image Processing (A+)

   • Achieved optimal solutions for picture contrast and smoothness using MATLAB programming
   • Demonstrated proficiency in understanding and deriving the optimal solution formula from the professor's published paper.
   • Produced significantly superior results compared to traditional methods in image processing.

6. M.S. in Imperial College London- Analogue and Digital Integrated Circuit Design - Full-Custom Integrated Circuit Design

   • Successfully realized a 10-bit current-steering binary-weighted Digital-to-Analog Converter (DAC).
   • Delved into CMOS technology, understanding its key features and limitations in analog, digital, and mixed-signal integrated circuits.
   • Mastered the methodology of full-custom chip design, addressing issues and constraints in analog, digital, and mixed-signal circuit design.
   • Designed and evaluated layouts for full-custom integrated circuits, utilizing a comprehensive tool suite for CMOS integrated circuit full-custom design (schematic capture, simulation, layout design).
   • Designed the digital section for serial-to-parallel conversion of signals and control signal processing, based on D flip-flops and digital logic combinations like NOR and NAND.
   • Completed the analog part of a DAC, employing a more precise current source architecture based on binary-weighted low-voltage cascode current mirror.
   • The chip drew only 2mW from a single 1.2V supply plus load currents, with an output range from 0.1V to 1.1V.
   • Achieved an INL below 2.2 LSBs and a DNL below 1.75 LSBs.
   • The layout design utilized a maximum of four metal layers and occupied an area below 0.03 mm2.
   • Conversion rate exceeded 400KHz.

7. M.S. in Imperial College London- Analogue and Digital Integrated Circuit Design - Hardware and Software Verification

   • To be added

8. M.S. in Imperial College London- Analogue and Digital Integrated Circuit Design - ADIC Laboratory Experiments

   • To be added

9. M.S. in Imperial College London- Analogue and Digital Integrated Circuit Design - Advanced Digital Systems Design

   • To be added

10. M.S. in Imperial College London- Analogue and Digital Integrated Circuit Design - Advanced Electronic Devices

    • To be added

11. M.S. in Imperial College London- Analogue and Digital Integrated Circuit Design - Instrumentation

    • To be added

12. M.S. in Imperial College London- Analogue and Digital Integrated Circuit Design - Graduation Project

    • Deep Learning-Based Glucose Prediction Using Bluetooth Low Energy(Graduation Thesis)
    • To be added

Skills