FIFO FWFT Adapter(First Word Fall Through) 预读FIFO适配器

wymvelyaten / 2023-07-31 / 原文


`timescale 1ns / 1ps
/*========================================FILE_HEADER=====================================
# Author          : WYM
# Create Time     : 2023-07-31 15:32
# Last modified   : 2023-07-31 15:32
# Filename        : fwft_adapt.sv
# Synthesizable   :  Vivado 2022.2
# FPGA Chip Model :  XC7A100T-2
# Description     : fwft_adapt.sv
#
#
=========================================FILE_HEADER====================================*/
module fwft_adapt
#(
    parameter DATA_WIDTH = 8
)
(
    input rclk,
    input rst,
    input rden,
    output empty,
    output [DATA_WIDTH - 1 : 0]dout,
    input fifo_empty,
    output fifo_rden,
    input [DATA_WIDTH - 1 : 0]fifo_din
);

    reg pre_reg_ld = 0;
    reg pre_reg_ld_d = 0;
    reg pre_reg_ld_dd = 0;

    reg [DATA_WIDTH - 1 : 0]dout_d;
    reg [DATA_WIDTH - 1 : 0]dout_dd;

    assign fifo_rden = ~fifo_empty & (~pre_reg_ld_dd | rden);

    always@(posedge rclk)
        if(rst)
        begin
            pre_reg_ld <= 0;
            pre_reg_ld_d <= 0;
            pre_reg_ld_dd <= 0;
        end
        else
        begin
            pre_reg_ld <= fifo_rden;
            pre_reg_ld_d <= pre_reg_ld;
            pre_reg_ld_dd <= pre_reg_ld_d;
        end

    assign empty = ~pre_reg_ld_dd;

    always@(posedge rclk)
    begin
        if(pre_reg_ld)
            dout_d <= fifo_din;
        if(pre_reg_ld_d)
            dout_dd <= dout_d;
    end

    assign dout = dout_dd;

endmodule