《Clock Domain Crossing》 总结 （1）亚稳态
1. 亚稳态的定义
亚稳态是指在设计正常操作的某个持续时间内，信号无法确定处于0还是1状态。在多时钟设计中，亚稳态无法避免，但可以亚稳态的不利影响可以被消除。
Figure 1 shows a synchronization failure that occurs when a signal generated in one clock domain is sampled too close to the rising edge of a clock signal from a second clock domain. Synchronization failure is caused by an output going metastable and not converging to a legal stable state by the time the output must be sampled again.
1. 亚稳态的定义
亚稳态是指在设计正常操作的某个持续时间内，信号无法确定处于0还是1状态。在多时钟设计中，亚稳态无法避免，但可以亚稳态的不利影响可以被消除。
2. 亚稳态的影响
为什么亚稳态是一个问题呢？Figure